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rt9199 1 ds9199-07 september 2007 www.richtek.com pin configurations cost-effective, 2a peak sink/source bus termination regulator ordering information general description the rt9199 is a simple, cost-effective and high-speed linear regulator designed to generate termination voltage in double data rate (ddr) memory system to comply with the devices requirements. the regulator is capable of actively sinking or sourcing up to 2a peak while regulating an output voltage to within 20mv. the output termination voltage can be tightly regulated to track 1/2v ddq by two external voltage divider resistors or the desired output voltage can be pro-grammed by externally forcing the refen pin voltage. the rt9199 also incorporates a high-speed differential amplifier to provide ultra-fast response in line/load transient. other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. the rt9199 are available in both sop-8 and sop-8 (exposed pad) surface mount packages. features z z z z z ideal for ddr-ii v tt applications z z z z z sink and source 2a peak current z z z z z integrated power mosfets z z z z z generate termination voltage for ddr memory interfaces z z z z z high accuracy output voltage at full-load z z z z z output adjustment by two external resistors z z z z z low external component count z z z z z shutdown for suspend to ram (str) functionality with high-impedance output z z z z z current limiting protection z z z z z on-chip thermal protection z z z z z rohs compliant and 100% lead (pb)-free applications z desktop pcs, notebooks, and workstations z graphics card memory termination z set top boxes, digital tvs, printers z embedded systems z active termination buses z ddr/ii memory systems (top view) sop-8 sop-8 (exposed pad) note : richtek pb-free and green products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. ` 100%matte tin (sn) plating. vin gnd refen vout vcntl 2 3 4 5 6 7 8 vcntl vcntl vcntl package type s : sop-8 sp : sop-8 (exposed pad-option 2) rt9199 operating temperature range p : pb free with commercial standard g : green (halogen free with commer- cial standard) vin gnd refen vout nc nc nc vcntl gnd 2 3 4 5 6 7 8 9
rt9199 2 ds9199-07 september 2007 www.richtek.com typical application circuit r 1 = r 2 = 100k , r tt = 50 / 33 / 25 c out(min) = 10 f (ceramic) + 1000 f under the worst case testing condition r dummy = 1k as for v out discharge when v in is not presented but v cntl is presented c ss = 1 f, c in = 470 f (low esr), c cntl = 47 f vin refen gnd vcntl vout rt9199 en 2n7002 r 1 r 2 c ss v in = 1.8v v cntl = 5v c cntl c in r tt c out r dummy test circuit figure 1. output voltage tolerance, v load figure 2. current in shutdown mode, i stby vin refen gnd vcntl vout rt9199 1.25v c out i l v out v v in = 1.8v v cntl = 5v vin refen gnd vcntl vout rt9199 v in = 1.8v 0.9v c out v out v r l 0.9v 0v r l and c out time deleay 0.15v a v cntl = 5v
rt9199 3 ds9199-07 september 2007 www.richtek.com figure 3. current limit for high side, i lim figure 4. current limit for low side, i lim figure 5. refen pin shutdown threshold, v ih & v il vin refen gnd vcntl vout rt9199 0.9v c out i l v out v a v in = 1.8v v cntl = 5v vin refen gnd vcntl vout rt9199 v in = 1.8v 0.9v c out i l v out v a power supply with current limit v cntl = 5v vin refen gnd vcntl vout rt9199 v in = 1.8v c out v out v r l 0.9v 0v r l and c out time deleay 0.9v 0.15v v out v refen v out would be low if v refen < 0.15v v out would be high if v refen > 0.6v v cntl = 5v
rt9199 4 ds9199-07 september 2007 www.richtek.com functional pin description vin input voltage which supplies current to the output pin. connect this pin to a well-decoupled supply voltage. to prevent the input rail from dropping during large load transient, a large, low esr capacitor is recommended to use. the capacitor should be placed as close as possible to the vin pin. gnd (exposed pad) common ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. vcntl vcntl supplies the internal control circuitry and provides the drive voltage. the driving capability of output current is proportioned to the vcntl. connect this pin to 5v bias supply to handle large output current with at lea st 1 f capacitor from this pin to gnd. an important note is that vin should be kept lower or equal to vcntl. refen reference voltage input and active low shutdown control pin. two resistors dividing down the vin voltage on the pin to create the regulated output voltage. pulling the pin to ground turns off the device by an open-drain, such as 2n7002, signal n-mosfet. vout regulator output. vout is regulated to refen voltage that is used to terminate the bus resistors. it is capable of sinking and sourcing current while regulating the output rail. to maintain adequate large signal transient response, typical value of 1000 f al electrolytic capacitor with 10 f ceramic capacitors are recommended to reduce the effects of current transients on vout. function block diagram gnd vcntl refen current limit thermal protection vout ea + - vin
rt9199 5 ds9199-07 september 2007 www.richtek.com electrical characteristics (v in = 1.8v, v cntl = 5v, v refen = 0.9v, c out = 10 f (ceramic), t a = 25c, unless otherwise specified) parameter symbol test conditions min typ max units input vcntl operation current i cntl i out = 0a -- 1 2.5 ma standby current (note 7) i stby v refen < 0.2v (shutdown), r load = 180 -- 2 90 a output (ddr ii) output offset voltage (note 5) v os i out = 0a ? 20 -- +20 mv i out = +1.8a load regulation (note 6) v load i out = ? 1.8a ? 20 -- +20 mv protection current limit i limit 2.0 -- 3.5 a thermal shutdown temperature t sd v cntl = 5v 125 170 -- c thermal shutdown hysteresis t sd v cntl = 5v -- 35 -- c refen shutdown v ih enable 0.6 -- -- shutdown threshold v il shutdown -- -- 0.15 v absolute maximum ratings (note 1) z input voltage, v in ------------------------------------------------------------------------------------------------------ 6v z control voltage, v cntl ----------------------------------------------------------------------------------------------- 6v z power dissipation, p d @ t a = 25 c sop-8 ------------------------------------------------------------------------------------------------------------------- 0.9 09w sop-8 (exposed pad ) ---------------------------------------------------------------------------------------------- 1.176w z package thermal resistance (note 4) sop-8, ja -------------------------------------------------------------------------------------------------------------- 110 c/w sop-8, jc -------------------------------------------------------------------------------------------------------------- 60 c/w sop-8 (exposed pad), ja ------------------------------------------------------------------------------------------ 86 c/w sop-8 (exposed pad), jc ----------------------------------------------------------------------------------------- 15 c/w z junction temperature ------------------------------------------------------------------------------------------------- 125 c z lead temperature (soldering, 10 sec.) --------------------------------------------------------------------------- 260 c z storage temperature range ---------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 2) hbm (human body mode) ------------------------------------------------------------------------------------------ 2kv mm (ma chine mode) -------------------------------------------------------------------------------------------------- 200v recommended operating conditions (note 3) z input voltage, v in ------------------------------------------------------------------------------------------------------ 1.6v to 5.5v z control voltage, v cntl ----------------------------------------------------------------------------------------------- 5v 5% z junction temperature range ---------------------------------------------------------------------------------------- ? 40 c to 125 c
rt9199 6 ds9199-07 september 2007 www.richtek.com note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. the device is not guaranteed to function outside its operating conditions. note 4. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity test board (4 layers, 2s2p) of jedec 51-7 thermal measurement standard. the case point of jc is on the exposed pad for sop-8 (exposed pad) package. note 5. v os offset is the voltage measurement defined as v out subtracted from v refen . note 6. regulation is measur ed at constant junction temperature by using a 5ms current pulse. devices are tested for load regulation in the load range from 0a to 2a peak. note 7. standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on refen pin (v il < 0.15v). it is measured with v in = v cntl = 5v.
rt9199 7 ds9199-07 september 2007 www.richtek.com typical operating characteristics sink current limit vs. temperature 0 0.5 1 1.5 2 2.5 3 3.5 -50 -25 0 25 50 75 100 125 temperature source current limit (a) v in = 1.8v, v cntl = 5v ( c) source current limit vs. temperature 0 0.5 1 1.5 2 2.5 3 3.5 -50 -25 0 25 50 75 100 125 temperature source current limit (a) v in = 1.8v , v cntl = 5v ( c) vcntl pin current vs. temperature 0.1 0.2 0.3 0.4 0.5 0.6 -50 -25 0 25 50 75 100 125 temperature vcntl pin current (ma) v in = 1.8v, v cntl = 5v ( c) output voltage vs. temperature 0.88 0.885 0.89 0.895 0.9 0.905 0.91 0.915 0.92 -50 -25 0 25 50 75 100 125 temperature output voltage (v) v in = 1.8v, v cntl = 5v ( c) shutdown threshold vs. temperature 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 -50 -25 0 25 50 75 100 125 temperature shutdown threshold (v) ( c) rt9199 ? sp, v cntl = 5v turn on turn off vin current vs. temperature 0 0.5 1 1.5 2 2.5 3 -50 -25 0 25 50 75 100 125 temperature vin current (ma) v in = 1.8v, v cntl = 5v ( c)
rt9199 8 ds9199-07 september 2007 www.richtek.com 1.25v tt @ 1.8a transient response output voltage transient (mv) 50 0 -50 output current (a) 2 1 0 -1 -2 v in = 2.5v, v cntl = 5v, v out = 1.25v time (25 s/div) swing frequency : 10khz v in = 1.8v, v cntl = 5v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 time (1ms/div) sink v in = 2.5v, v cntl = 5v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 time (1ms/div) sink v in = 1.8v, v cntl = 5v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 time (1ms/div) source v in = 2.5v, v cntl = 5v output short-circuit protection output short circuit (a) 12 10 8 6 4 2 0 time (1ms/div) source 0.9v tt @ 1.8a transient response output voltage transient (mv) 50 0 -50 output current (a) 2 1 0 -1 -2 v in = 1.8v, v cntl = 5v, v out = 0.9v time (25 s/div) swing frequency : 10khz
rt9199 9 ds9199-07 september 2007 www.richtek.com general regulator the rt9199 could also serves as a general linear regulator. the rt9199 accepts an external reference voltage at refen pin and provides output voltage regulated to this reference voltage as shown in figure 6, where v out = v refen x r2/(r1+r2) as other linear regulator, dropout voltage and thermal issue should be specially considered. figure 7 shows the r ds(on) over temperature of rt9199. the minimum dropout voltage could be obtained by the product of r ds(on) and output current. for thermal consideration, please refer to the relative sections . application information consideration while designing the resistance of voltage divider refer to the ? typical application circuit ? .make sure the current sinking capability of pull-down nmos is enough for the chosen voltage divider to pull-down the voltage at refen pin below 0.15v to shutdo wn the device. in addition, the capacitor c ss and volt age divider form the low-pass filter. there are two reasons doing this design; one is for output voltage soft-start while another is for noise immunity. how to reduce power dissipation on notebook pc or the dual channel ddr sdram application? in notebook application, using richtek's patent ? d istributed bus terminator topology ? with choosing richtek's product is encouraged. distributed bus terminating topology r0 r9 r8 r7 r6 r5 r4 r3 r2 r1 r(2n) r(2n+1) rt9199 rt9199 vout vout refen bus(0) bus(1) bus(2) bus(3) bus(4) bus(5) bus(6) bus(7) bus(8) bus(9) bus(2n) bus(2n+1) terminator resistor input capacitor and layout consideration place the input bypass capacitor as close as possible to the rt9199. a low esr capacitor larger than 470uf is recommended for the input capacitor. use short and wide traces to minimize parasitic resistance and inductance. inappropriate layout may result in large parasitic inductance and cause undesired oscillation between rt9199 and the preceding power converter. thermal consideration rt9199 regulators have internal thermal limiting circuitry designed to protect the device during overload conditions. for continued operation, do not exceed absolute maximum operation junction temperature 125 c. the power dissipation definition in device is: p d = (v in - v out ) x i out + v in x i q figure 6 vcntl refen gnd vin vout rt9199 v refen r1 r2 figure 7 r ds(on) vs. temperature 0.28 0.3 0.32 0.34 0.36 0.38 0.4 0.42 0.44 0.46 0.48 -50-250 255075100125 temperature r ds(on) ( ? ) v cntl = 5v , v refen = 1v ( c)
rt9199 10 ds9199-07 september 2007 www.richtek.com the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula: p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. the junction to ambient thermal resistance for sop-8 package (exposed pad) is 86 c/w, on standard jedec 51-7 (4 layers, 2s2p) thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula: p d(max) = (125 c ? 25 c) / 86 c/w = 1.163w figure 8 shows the package sectional drawing of sop-8 (exposed pad). every package has several thermal dissipation paths. as show in figure 9, the thermal resistance equivalent circuit of sop-8 (exposed pad). the path 2 is the main path due to these materials thermal conductivity. we define the exposed pad is the case point of the path 2. figure 8. sop-8 (exposed pad) package sectional drawing ambient molding compound gold line lead frame die pad case (exposed pad) pcb the thermal resistance ja of sop-8 (exposed pad) is determined by the package design and the pcb design. however, the package design has been decided. if possible, it ? s useful to increase thermal performance by the pcb design. the thermal resistance can be decreased by adding copper under the expose pad of sop-8 package. figure 10 show the relation between thermal resistance ja and copper area on a standard jedec 51-7 (4 layers, 2s2p) thermal test board at t a = 25 c. we have to consider the copper couldn ? t stretch infinitely and avoid the tin overflow. we use the ? dog-bone ? copper patterns on the top layer as figure 11. 0 10 20 30 40 50 60 70 80 90 100 0 1020304050607080 copper area (mm 2 ) thermal resistance ja (c/w) figure 10. relation between thermal resistance ja and copper area figure 11. dog-bone layout exposed pad w Q 2.28mm figure 9. thermal re sistance equivalent circuit junction r die r die-attach r die-pad r gold-line r lead frame case (exposed pad) r pcb r pcb ambient r molding-compound path 1 path 2 path 3
rt9199 11 ds9199-07 september 2007 www.richtek.com as shown in figure 12, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad of 2 oz. copper (figure 12.a), ja is 86 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 12.b) reduces the ja to 73 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 12.d) reduces the ja to 65 c/w. figure 12. thermal resistance vs. copper area layout thermal design (a) copper area = 10mm 2 , ja = 86 c/w (b) copper area = 30mm 2 , ja = 73 c/w (c) copper area = 50mm 2 , ja = 68 c/w (d) copper area = 70mm 2 , ja = 65 c/w
rt9199 12 ds9199-07 september 2007 www.richtek.com outline information a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050
rt9199 13 ds9199-07 september 2007 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 8f, no. 137, lane 235, paochiao road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)89191466 fax: (8862)89191465 email: marketing@richtek.com a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package symbol dimensions in millimeters dimensions in inches min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 option 1 x 2.000 2.300 0.079 0.091 y 2.000 2.300 0.079 0.091 option 2 x 2.100 2.500 0.083 0.098 y 3.000 3.500 0.118 0.138

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